Storage subsystem

ABSTRACT

The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.

CROSS-REFERENCE

This is a continuation of U.S. Ser. No. 12/526,666, filed Aug. 11, 2009.This application claims priority from National Stage ofPCT/JP2009/059921, filed May 25, 2009. The entire disclosures of all ofthese applications are hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to a storage subsystem mounted withnonvolatile semiconductor memory such as flash memory in a storageapparatus.

BACKGROUND ART

In recent years, attention has focused on the flash memory, a typicalnonvolatile semiconductor memory, for storage devices. Because a flashmemory does not have a drive portion like a magnetic storage devicetypified by a HDD (Hard Disk Drive), it features lower power consumptionthan a HDD. A storage device that uses a memory drive mounted with aplurality of flash memories instead of a HDD has been proposed as anexternal storage device (refer to Patent Document 1).

Meanwhile, a storage subsystem must be stable, and as such, employs aconfiguration with duplexed components that enables processing to becarried out even when a malfunction occurs in a portion of thecomponents. For example, in order to heighten data integrity andthroughput, RAID (Redundant Array of Inexpensive Disks) technology isused to manage a plurality of storage devices as a single RAID Group,and to redundantly store data. The RAID Group forms one or more logicalstorage areas at this time. When data is stored in the storage area,redundant data is stored in the storage devices configuring the RAIDGroup. Storing redundant data in the storage devices makes it possibleto recover the data even when one of the storage devices malfunctions.

For example, in a case where a memory drive comprising flash memories isconfigured as RAID 5, a ECC (Error Correct Code) computed using aplurality of data is stored in an ECC memory drive, and even if onememory drive should malfunction, it is possible to recover the datastored in the failed memory drive by using the remaining data and theECC.

However, if malfunctions should occur in more than a predeterminednumber of memory drives, it becomes impossible to recover the data evenin a RAID-configured subsystem. Accordingly, a storage subsystemgenerally makes use of an extra drive in which data has not been stored,called a spare drive.

The storage subsystem employs a configuration in which, in a case wherea malfunction occurs in one of the RAID-configured memory drives, thedata in the failed memory drive is recovered using the data in theremainder of the RAID-configured memory drives, and is stored in thespare drive.

[Patent Document 1]

Japanese Patent Application Laid-open No. 2008-204041

In a RAID 5-configured storage subsystem, for example, when data a, b, cis written to a storage device during an initial data write, the data a,b, c is respectively stored in three HDD or memory drives, a parity iscreated by using the data a, b, c to carry out an exclusive ORoperation, and the created parity is stored in either a HDD or memorydrive designated for storing the parity.

The configuration is such that a processor for controlling theinput/output of data to/from the storage devices at this time createsthe parity by using the data a, b, c in a cache memory to carry out theexclusive OR operation, and stores the created parity in either theparity-storage-designated HDD or memory drive.

During a random write in line with a data update, the processor uses anexclusive OR operation to create a new parity based on the old data,which has been targeted for updating, new data and the old parity (theparity corresponding to the old data), and stores the created new parityin either the HDD or memory drive designated for parity storage.

However, when updating HDD data, the HDD data may be overwritten. Forthis reason, there is the possibility of the old parity stored in theHDD being lost as a result of the overwrite process. When this happens,it is not possible to use the old parity to create a new parity whenupdating HDD data.

By contrast, when updating flash memory data, new data is written to theupdate region as new data, and the old data targeted for updatingremains until the entire block is deleted. For this reason, the newparity stored in the memory drive also remains as-is until the block isdeleted in its entirety. In this case, it is possible to use the oldparity to create the new parity when updating flash memory data.

However, in a configuration in which the processor uses cache memory tocarry out an operation for creating the new parity, the processoraccesses the cache memory many times, making it impossible to reduce theload on the processor.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a storage subsystemthat makes it possible to carry out the processing accompanying a dataupdate by distributing this processing between a control unit thatcontrols a cache memory and a memory controller that controls anonvolatile semiconductor memory.

To achieve the above-mentioned object, the present invention ischaracterized in that, when updating data in a nonvolatile semiconductormemory, the present invention creates a command for data updating in thecontrol unit that controls the cache memory, transfers the createdcommand from the control unit to the memory controller that controls thenonvolatile semiconductor memory, creates a new parity by carrying outan exclusive OR operation in the memory controller on the basis of thiscommand, and stores the created new parity in the nonvolatilesemiconductor memory provided for storing parity.

According to the present invention, when updating data in a nonvolatilesemiconductor memory, it is possible to lessen the load on the controlunit that controls the cache memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a storage system showing a first embodimentof the present invention;

FIG. 2 is a block diagram of a flash module;

FIG. 3 is a block diagram of a flash memory controller;

FIG. 4 is a block diagram of a flash memory;

FIG. 5 is a diagram of a block of a memory cell array;

FIG. 6(A) is a circuit diagram of a memory cell, and FIG. 6(B) is acircuit diagram illustrating the cell structure of the memory cell;

FIG. 7 is a diagram illustrating a sequential write process;

FIG. 8(A) is a diagram of an XOR write command for an HDD, and FIG. 8(B)is a diagram of an XOR write command for a flash memory;

FIG. 9 is a diagram illustrating the operation during a random write toan HDD;

FIG. 10 is a diagram illustrating the operation during a random write toa flash memory;

FIG. 11 is a diagram illustrating a method for storing parity in arenewal area of one sector's worth of a page;

FIG. 12 is a flowchart explaining the working of the first embodiment ofthe present invention;

FIG. 13 is a diagram illustrating a reclamation process;

FIG. 14 is a block diagram of a flash memory controller used in a secondembodiment of the present invention; and

FIG. 15 is a flowchart explaining the working of the second embodimentof the present invention.

EXPLANATION OF REFERENCE NUMERALS

-   10 UPPER HOST SYSTEM-   12 STORAGE SUBSYSTEM-   14 NETWORK-   16 UPPER HOST SYSTEM INTERFACE UNIT-   18 MAIN PROCESSOR-   20 SWITCH-   22 CACHE-   24 DISK DRIVE CONTROL UNIT-   26 STORAGE APPARATUS-   38 HDD-   40 FLASH MODULE-   42 FLASH MEMORY CONTROLLER-   44 FLASH MEMORY-   48 MICROPROCESSOR-   50 RAM-   52 ROM-   64 FLASH MEMORY CHIP-   70 BLOCK-   72 PAGE-   74 USER AREA-   76 RENEWAL AREA

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1

This embodiment is configured such that during a random write, the mainprocessor, which controls the cache, creates an XOR write command at thetime the update data is written to the flash module, and transfers thecreated XOR write command to the flash memory controller that controlsthe flash memory, the flash memory controller parses the XOR writecommand, reads out the old parity from the parity-storage flash memory,creates a new parity by carrying out an exclusive OR operation using theread-out old parity and the old data and new data added to the XOR writecommand, and stores the created new parity in the parity-storage flashmemory.

The first embodiment of the present invention will be explained belowbased on the drawings. FIG. 1 is a block diagram of a storage systemshowing the first embodiment of the present invention.

In FIG. 1, the storage system comprises a plurality of upper hostsystems 10 and a storage subsystem 12, and each upper host system 10 isconnected to the storage subsystem 12 via a network 14.

For example, a SAN (Storage Area Network), LAN (Local Area Network), theInternet, a leased line, a public telephone network, or any datacommunication-enabled network may be used as the network 14. Also, thefibre channel protocol, or the TCP/IP protocol may be used as theprotocol for the network 14, and even an arbitrary protocol may be usedas long as the protocol enables the exchange of data between the upperhost systems 10 and the storage subsystem 12.

The upper host system 10 comprises a host computer (not shown in thedrawing). The host computer, for example, comprises a CPU (CentralProcessing Unit), a memory, an input device, an output device, and ahost adapter. The CPU creates a read request (read command) and a writerequest (write command) in accordance with an application program storedin the memory, and sends same from the host adapter. A LUN (Logical UnitNumber) and a LBA (Logical Block Address), via which read-targeted datais managed, are included in a read request sent from the upper hostsystem 10 at this time. Further, for example, a LUN and a LBA, to whichwrite-targeted data is written, and write-targeted data are included ina write request sent from the upper host system 10.

The storage subsystem 12 comprises a plurality of upper host systeminterface units 16; a plurality of main processors 18; a switch 20; aplurality of cache memories (referred to as cache hereinafter) 22; aplurality of disk drive control units 24; and a plurality of storageapparatuses 26, and a logical volume constructed in accordance with therespective storage apparatuses 26 may be provided to the respectiveupper host systems 10 via the network 14.

Each upper host system interface unit 16 is connected to the switch 20by way of an internal network 28, each main processor 18 is connected tothe switch 20 by way of an internal network 30, and each cache 22 isconnected to the switch 20 by way of an internal network 32. The switch20 is connected to the respective disk drive control units 24 by way ofan internal network 34, and the respective disk drive control units 24are connected to the respective storage apparatuses 26 by way of aninternal network 36.

Each upper host system interface unit 16 is configured as a firstinterface unit for exchanging information with the respective upper hostsystems 10 via the network 14, and carrying out data input/outputprocessing for the respective upper host systems 10.

Each main processor 18, as a control unit for controlling the storageapparatuses 26 and the caches 22, executes a variety of operations inaccordance with commands from a program or the respective upper hostsystems 10, and, for example, the processes accompanying a controloperation or random write for controlling the caches 22 and the storageapparatuses 26. At this time, the respective main processors 18temporarily store the data associated with processing in the cache 22,and execute data input-output processing using the cache 22-stored data.

Each disk drive control unit 24 is configured as a second interface unitfor exchanging information with the respective main processors 18 viathe switch 20, exchanging information with the respective storageapparatuses 26 via an internal network 36, and carrying out datainput/output processing with respect to the groups of storage devicesinside the storage apparatuses 26.

The storage apparatus 26 comprises a plurality of HDD 38 and alsocomprises a plurality of flash modules 40, and the plurality of HDD 38is configured as a disk array and the plurality of flash modules 40 isconfigured as a flash module array.

At this time, either a logical device (VDEV: Virtual Device) or alogical volume, which is a logical storage device capable of beingreferenced from the upper host system 10, may be allocated to a storagearea of either the respective HDD 38 or the respective flash modules 40.In accordance with this, in a case where a RAID (Redundant Array ofInexpensive Disks) Group is configured by the plurality of HDD 38 or theplurality of flash modules 40, the RAID Group storage area may also beutilized as either the logical device or the logical volume storagearea.

Each flash module 40, as shown in FIG. 2, comprises a flash memorycontroller 42 and a plurality of flash memories 44. Each flash memory 44is connected to the flash memory controller 42 via a bus 46, and theflash memory controller 42 is connected to the disk drive control unit24 via the internal network 36.

The flash memory controller 42, as shown in FIG. 3, comprises amicroprocessor (MPU: Microprocessing Unit) 48; a RAM (Random AccessMemory) 50; a ROM (Read Only Memory) 52; a host interface 54; and aflash memory interface 56. The microprocessor 48, RAM 50 and ROM 52 arerespectively connected to a bus 58, and the host interface 54 and flashmemory interface 56 are connected to a bus 60. The host interface 54 isconnected to the disk drive control unit 24 via the internal network 36,and is also connected to the microprocessor 48, RAM 50 and ROM 52 viathe bus 58. The host interface 54 is connected to the flash memoryinterface 56 via the bus 60, and the flash memory interface 56 isconnected to the respective flash memories 44 via the bus 46.

The host interface 54, under the control of the microprocessor 48,executes data input/output processing to/from the disk drive controlunit 24 via the internal network 36. The flash memory interface 56,under the control of the microprocessor 48, executes data input/outputprocessing to/from the respective flash memories 44 via the bus 46. Atthis time, a direct memory access controller (DMAC) 62, which is builtinto the host interface 54, executes external data input/outputprocessing to/from the flash memories 44 without relying on the controlof the microprocessor 48.

The microprocessor 48, as an auxiliary processor, executes various typesof operational processing in accordance with a program stored in the ROM52, parses a command inputted from the host interface 54, stores theresults of parsing in the RAM 50, and also executes an operationalprocess in accordance with the parsing result, and controls theinput/output processing of data to/from the respective flash memories 44by way of the flash memory interface 56.

As shown in FIG. 4, each flash memory 44 comprises a flash memory chip64, and a memory cell array 66 and internal buffer 68 are formed in theflash memory chip 64. Between several thousands and several hundreds ofthousands of blocks 70, which constitute data erase units, are formed inthe memory cell array 66, and a plurality of pages 72, which constituteeither data read or data write units, is formed in each block 70.

A chip select line 461, a control line 462, and a ready/busy line 463are connected to this flash memory chip 64 as signal lines belonging tothe bus 46. In addition, an 8-bit I/O line 464 is connected to theinternal buffer 68 as a signal line belonging to the bus 46.

Each block 70, as shown in FIG. 5, comprises a user area 74; and arenewal area 76. The user area 74 is divided into pages 72 numbered from#0 through #95, and the renewal area 76 is divided into pages 72numbered from #96 through #127. The physical address of the respectivepages 72 #0 through #127 are set to #0 through #127.

Data 78 numbered #0 through #95 is stored in pages 72 numbered #0through #95, and metadata 80 is also stored in each of these pages 72 asmanagement information for managing the respective data 78.

Conversely, the renewal area 76 is a storage area for storing data atupdate time. For this reason, pages 72 numbered #96 through #127 of therenewal area 76 are empty prior to data updating.

As shown in FIGS. 6(A) and (B), each block 70 comprises a plurality ofmemory cells 82, and the respective memory cells 82 are arrayed in alattice-like pattern. A page 72 is comprised of one horizontal row ofthese memory cells 82. Each memory cell 82 is configured as afield-effect transistor 86 having a floating gate 84. A bit line 88 anda word line 90 are connected to each memory cell 82. The respective bitlines 88 and respective word lines 90 are arranged orthogonally to oneanother.

In the above-mentioned configuration, a given main processor 18 parses acommand from the upper host system 10, and based on this parsing result,carries out processing for converting the logical address added to thecommand to a physical address in accordance with a conversion table,and, in addition, carries out input/output processing to/from thestorage apparatus 26. As shown in FIG. 7, for example, when writing in“a”, “b” and “c” data 78 during a sequential write, which is when thedata is initially written in, processing is carried out for writing the“a” data 78 to the #1 HDD 38, the “b” data 78 to the #2 HDD 38, and the“c” data 78 to the #3 HDD 38, respectively. In addition, the mainprocessor 18 executes processing for creating a parity 92 based on the“a” through “c” data 78, and for writing the parity 92 to the #4 HDD 38.

That is, the main processor 18 carries out an operation for creating aparity 92, and, in addition, transfers the created parity 92 to the diskdrive control unit 24 together with the “a”, “b” and “c” data 78, andprovides to the disk drive control unit 24 instructions to store the“a”, “b” and “c” data 78 and the parity 92 in specified HDD 38.

In accordance with this, when respectively distributing and storing the“a”, “b” and “c” data 78 and the parity 92 in the flash modules 40, themain processor 18 also carries out an operation for creating a parity92, and thereafter furnishes an instruction to the flash memorycontroller 42 via the disk drive control unit 24 to respectivelydistribute and store the “a”, “b” and “c” data 78 and the parity 92 inthe #1 through #4 flash modules 40.

Conversely, during a random write, the main processor 18 executes an XORwrite in accordance with an XOR write command 94 as shown in FIG. 8(A).The XOR write command 94 is configured from a logical block address(LBA) 941, a size 942, data 943, and a check code 944.

When updating data during a random write, for example, when the “b” data78 is regarded as the old data, the “d” data 78 is regarded as the newdata, and the old data is updated to the new data as shown in FIG. 9,the main processor 18 executes an XOR (Exclusive OR) write operation forretrieving the parity 92 from the #4 HDD 38 as the old parity 96,retrieving the “b” data 78 from the #2 HDD 38 as the old data, creatinga new parity 98 by carrying out an exclusive OR operation based on the“b” data 78, the “d” data 78 and the old parity 96, and writing the newparity 98 to the #4 HDD 38.

Conversely, when writing update data to the flash module 40 during arandom write, the main processor 18 does not carry out an operation forcreating a new parity 98, but rather, as shown in FIG. 8(B), creates anXOR write command 100, and transfers the created XOR write command 100to the flash memory controller 42 via the disk drive control unit 24.

The XOR write command 100 at this time is configured from flash memoryaddress 1001, which constitutes the physical address of the old parity96, flash memory address 1002, which constitutes the physical address ofthe new parity 98, size/number 1003, data 1004, data 1005, and a checkcode 1006.

In a case where the flash memory controller 42 updates the “b” data 78stored in the #2 flash module 40 as the old data, and the “d” data 78 asthe new data as shown in FIG. 10, the flash memory controller 42 readsout the old parity 96 stored in the #4 flash module (parity storageflash module) 40, carries out an exclusive OR operation using theread-out old parity 96, the “b” data 78, and the “d” data 78 to create anew parity 98, and executes an XOR write process for the created newparity 98 to a page of the renewal area 76 of FIG. 5, for example, the#96 page 72.

That is, barring an erase operation having been carried out for theblock 70 where the old parity 96 exists, the old parity 96 exists in the#4 flash module 40, and the flash memory controller 42 uses the oldparity 96 to carry out an exclusive OR operation to generate the newparity 98.

In this case, the main processor 18 may simply create the XOR writecommend 100 and transfer the created XOR write command 100 to the flashmemory controller 42 by way of the disk drive control unit 24 withouthaving to use the cache 22 to carry out a parity creation operation,making it possible to lessen the processing (load) at the time of arandom write to the flash module 40.

Further, within the XOR write command 100, the physical address of theold parity 96 is stored in flash memory address 1001, the physicaladdress of the new parity 98 is stored in flash memory address 1002, the“b” data 78, which is the old data, is stored in data 104, and the “d”data 78, which is the new data, is stored in data 1005.

The microprocessor 48 of the flash memory controller 42 parses the XORwrite command 100, and, as shown in FIG. 11, reads out the old parity 96from the page 72 of the user area 74 of the flash memory 44 that belongsto the #4 flash module 40 in accordance with the physical address thathas been added to the flash memory address 1001, creates a new parity 98by carrying out an exclusive OR operation using the read-out old parity96, the “b” data 78, which is the old data that has been added to data1004, and the “d” data 78, which is the new data that has been added todata 1005, and stores the created new parity 98 in a micro-area 761 ofthe specified page 72 from among the #96 through #127 pages 72 belongingto the renewal area 76 in accordance with the physical address that hasbeen added to the flash memory address 1002.

As described hereinabove, when writing update data to a flash module 40during a random write, the main processor 18 may simply create the XORwrite command 100 and transfer the created XOR write command 100 to theflash memory controller 42 by way of the disk drive control unit 24.

The microprocessor 48 of the flash memory controller 42 then parses theXOR write command 100, reads out the old parity 96 from the page 72 ofthe user area 74 of the flash memory 44, creates a new parity 98 bycarrying out an exclusive OR operation using the read-out old parity 96,the “b” data 78, which is the old data that has been added to the XORwrite command 100, and the “d” data 78, which is the new data that hasbeen added to the XOR write command 100, and stores the created newparity 98 in the specified page 72 of the renewal area 76 in accordancewith the physical address that has been added to the XOR write command100.

Next, the processing of the main processor 18 during a random write willbe explained in accordance with the flowchart of FIG. 12. First, as theXOR write process for the flash module 40, the main processor 18 createsthe XOR write command 100, transfers the created XOR write command 100to the flash memory controller 42 by way of the disk drive control unit24 (S1), and determines whether or not an error occurred in the flashmodule 40 (S2). When an error has not occurred, the main processor 18ends the processing of this routine on the basis of the determinationthat the XOR write process has ended normally in the flash module 40,and when an error has occurred, carries out processing corresponding tothe nature of the error.

Specifically, when an error status is sent from the flash memorycontroller 42 within a set time period (S3), the main processor 18executes a reclamation process on the basis of the determination thatthe new parity 98 could not be written to the renewal area 76 (S4).

When a reclamation process is carried out, the main processor 18, asshown in FIG. 13, carries out processing to collect the latest data 78from the block 70, to retrieve the collected latest data 78 to a buffer18A inside the main processor 18, and to write the latest data 78retrieved to the buffer 18A to an erased block 70A. Since the logicaladdress and physical address of the latest data 78 change at this time,the main processor 18 carries out processing for updating the conversiontable to convert the logical address to the physical address.

Thereafter, as processing for retrying the new parity 98 write to therenewal area 76, the main processor 18 creates a new XOR write command100, transfers the created XOR write command 100 to the flash memorycontroller 42, and retries XOR write processing for the flash memorycontroller 42 (S5). Thereafter, the main processor 18 returns once againto the processing of Step S2, and determines whether or not an error hasoccurred in the flash module 40.

When it is determined in Step S2 that an error has occurred and theerror status has not been returned after the passage of a fixed timeperiod, the main processor 18 executes a time out process (S6) on thebasis of the determination that processing has been cancelled, andcarries out a process for checking the flash module 40 (S7).

When checking the flash module 40, the main processor 18 determineswhether or not the error occurred in the flash memory controller 42(S8), and when the determination is that the error did occur in theflash memory controller 42, executes a correction copy (S9).

That is, when an error has occurred in the flash memory controller 42and the error status has not been returned after the passage of a fixedtime period, the main processor 18 determines that the parity-storageflash memory 44 itself has malfunctioned, and carries out processing forcreating a parity 92 from three pieces of data, for example, the “a”,“b” and “c” data 78, and copying the created parity 92 to theparity-storage flash memory 44.

Thereafter, the main processor 18 retries the processing for the sameXOR write as that in Step S1 (S10), and returns to the processing ofStep S2.

When the determination in Step S8 is that there is no error in the flashmemory controller 42, that is, when processing is normal, the mainprocessor 18 carries out processing for checking the new parity 98written to the renewal area 76 in the parity-storage flash memory 44(S11), and makes a determination as to whether or not there is an errorin the ECC that has been added to the new parity 98 (S12). When thedetermination at this time is that there is no error in the ECC, thatis, when processing is normal, the main processor 18 decides that XORwrite processing has ended normally simply by virtue of the fact that astatus has not been returned from the flash memory controller 42,carries out processing performed when the XOR write process has endednormally (S13), and ends the processing of this routine.

Conversely, when it has been determined in Step S12 that an error hasoccurred in the ECC, the main processor 18 determines whether or not therenewal area 76 in the parity-storage flash memory 44 was erased on thebasis of the determination that the error occurred in the ECC (S14).When the determination here is that the parity-storage flash memory 44was erased, the main processor 18 decides that the XOR write itself wasnot possible, executes processing for retrying the XOR write to the samepage 72 of the renewal area 76 in the parity-storage flash memory 44(S15), and returns once again to Step S2.

When the determination in Step S14 is that the parity-storage flashmemory 44 has not been erased, the main processor 18 carries out, on thebasis of the decision that the parity write ended part way through theprocess, processing for retrying the XOR write to a new page of therenewal area 76 in the parity-storage flash memory 44 (S16), and returnsto the processing of Step S2.

When the status showing the completion of the XOR write is not returnedfrom the flash memory controller 42 like this, the main processor 18checks the flash module 40 targeted for the XOR write, and when amalfunction has occurred in the flash module 40 and it is not possibleto access the flash module 40 normally even when the power is ON,recovers parity by carrying out a correction copy to the spare flashmodule 40.

In a case where processing has ended part way through due to the factthat the power to the flash module 40 was cut off, the main processor 18calls up the new parity 98, checks the data and ECC, and makes adetermination as to whether the new parity 98 has yet to be written, anerror has occurred part way through the new parity 98 write, or writingof the new parity 98 has been completed.

Then, the main processor 18 carries out a retry (performs XOR writeprocessing once again) to the same page when the new parity 98 has yetto be written, carries out a retry to a new renewal area 76 when the newparity 98 write was in progress, and determines that the power was shutoff immediately prior to the completion status having been sent to themain processor 18 and regards the XOR write as having been completednormally when the new parity 98 write has been completed.

In this embodiment, when writing update data to the flash module 40during a random write, the main processor 18 creates the XOR writecommand 100, transfers the created XOR write command 100 to the flashmemory controller 42 by way of the disk drive control unit 24, and themicroprocessor 48 of the flash memory controller 42 parses the XOR writecommand 100, reads out the old parity 96 from the page 72 of the userarea 74 in the flash module 44, creates a new parity 98 by carrying outan exclusive OR using the read-out old parity 96, the “b” data 78, whichis the old data that has been added to the XOR write command 100, andthe “d” data 78, which is the new data that has been added to the XORwrite command 100, and stores the created new parity 98 in the specifiedpage 72 of the renewal area 76.

According to this embodiment, when writing update data to the flashmodule 40 during a random write, the main processor 18 simply createsthe XOR write command 100 and transfers the created XOR write command100 to the flash memory controller 42 by way of the disk drive controlunit 24, making it possible to lessen the processing (load) of the mainprocessor 18.

Embodiment 2

Next, a second embodiment of the present invention will be explained inaccordance with FIG. 14. This embodiment is configured such that aNV-RAM (Non Volatile Random Access Memory) 110 is disposed as a statusrecording memory in the flash memory controller 42 and a conversiontable for converting a logical address to a physical address is storedin the RAM 50, the contents of the conversion table are updated in aprocess in which the microprocessor 48 carries out input/outputprocessing to/from the respective flash modules 40 and the processingstatus is also sequentially recorded in the NV-RAM 110, and the recordedcontent is transferred to the main processor 18 by way of the hostinterface 54 making it possible for processing to commence from theplace instructed in instruction information from the main processor 18even when a malfunction occurs part way through the processing. Theremainder of the configuration is the same as that of the firstembodiment.

Next, the processing of the microprocessor 48 will be explained inaccordance with the flowchart of FIG. 14. First, the microprocessor 48of the flash memory controller 42 carries out processing for reading outthe old parity 96 (S21) and commences processing for creating the newparity 98 (S22) prior to starting the XOR write process. Thereafter, themicroprocessor 48 carries out processing for creating the new parity 98from two data, for example, the “b” and “d” data 78, and the old parity96 and storing the created new parity 98 in the page 72 of the renewalarea 76 in the parity-storage flash memory 44, and records the resultsof this processing in the NV-RAM 110 (S23).

Next, when the new parity 98 has been written to the specified page 72of the renewal area 76 in the parity-storage flash memory 44, themicroprocessor 48 records in the NV-RAM 110 that the new parity 98 writeis complete (S24), starts a process for updating the mapping of theconversion table stored in the RAM 50 (S25), and carries out processingfor moving a pointer in the conversion table.

Thereafter, when the movement of the pointer in the conversion table hasbeen completed, the microprocessor 48 records this in the NV-RAM 110(S26), carries out processing for responding to the main processor 18 tothe effect that the status is XOR write process complete (S27), and endsthe processing of this routine.

As described above, the microprocessor 48 records in the NV-RAM 110 atleast four status reports related to the XOR write process denoting newparity 98 write start, new parity 98 write complete, pointer renewal,and XOR write process complete, and transfers the recorded content tothe main processor 18, making it possible for the main processor 18 todetermine the state to which processing has transitioned in the flashmodule 40 that is the target of the XOR write process.

In accordance with this, the main processor 18 is able to prepareinstruction information corresponding to the microprocessor 48processing content based on the report transferred from themicroprocessor 48, and to send the prepared instruction information tothe microprocessor 48. Consequently, the microprocessor 48 is able tocontinue processing in accordance with the instruction information fromthe main processor 18 even in a case where the processing was cancelledpart way through.

For example, when processing is cancelled prior to the start of a newparity 98 write, the main processor 18 creates the instructioninformation for retrying the XOR write for the same page 72 of therenewal area 76 in the parity-storage flash memory 44, and transfersthis instruction information to the microprocessor 48.

Consequently, the microprocessor 48 is able to carry out the XOR writeretry for the same page 72 of the renewal area 76 in the parity-storageflash memory 44 in accordance with the instruction information from themain processor 18.

When processing is canceled prior to completion of the new parity 98write, the main processor 18 creates the instruction information forcarrying out an XOR write retry for a new page 72 of the renewal area 76in the parity-storage flash memory 44, and transfers this instructioninformation to the microprocessor 48. Consequently, the microprocessor48 is able to carry out the XOR write retry for a new page 72 of therenewal area 76 in the parity-storage flash memory 44 in accordance withthe instruction information from the main processor 18.

When processing is canceled prior to pointer renewal, the main processor18 creates instruction information for renewing the pointer, andtransfers this instruction information to the microprocessor 48.Consequently, the microprocessor 48 carries out pointer renewalprocessing in accordance with the instruction information from the mainprocessor 18.

When processing is canceled prior to the status report, the mainprocessor 18 creates instruction information to the effect that the XORwrite process was completed normally, and transfers this instructioninformation to the microprocessor 48. Consequently, the microprocessor48 determines that the XOR write process was completed normally.

In this embodiment, the microprocessor 48 is able to write a new parity98 to a page 72 of the renewal area 76 in the parity-storage flashmemory 44 on the bases of an XOR write command 100 from the mainprocessor 18, and by sequentially recording the processing status in theNV-RAM 110 and transferring the recorded content to the main processor18 during the steps for carrying out input/output processing to/from therespective flash modules 40, the microprocessor 48 is able to retryprocessing on the basis of instruction information from the mainprocessor 18.

According to this embodiment, it is possible to lessen the processing(load) of the main processor 18, and to retry processing on the basis ofinstruction information from the main processor 18.

1. A storage system comprising: a plurality of storage devices, each ofwhich includes a device controller configured to execute an XORoperation; and a storage controller configured to control the pluralityof storage devices as a RAID group, the plurality of storage devicesincludes a first storage device storing old data and a second storagedevice storing old parity corresponding to the old data, wherein thestorage controller is configured to read the old data from the firststorage device when the storage controller receives new data, which isto update the old data, and send the old data and the new data to thesecond storage device by using an XOR write command which instructsexecution of the XOR operation based on the old data, the new data andthe old parity.